The one-transistor storage cell for semiconductor dynamic random access memories (dRAMs) consists of a capacitor and an access transistor, controlled by a select signal (commonly referred to as a word line) for connecting one plate of the capacitor to a data line (commonly called the bit line). Conventional dRAMs are organized so that multiple storage cells are selected by the energizing of a word line, each of the selected cells communicating their contents to sense amplifiers by way of the associated bit line.
As for any integrated circuit, the trend for dRAMs is toward greater density of storage cells per unit area of semiconductor. However, the greater density of storage cells generally forces the storage cell capacitance to decrease. As the storage capacitance decreases, the amount of charge placed on the bit line by the storage capacitor decreases, resulting in a weaker signal for sensing by the sense amplifier, and also resulting in an increased sensitivity of the memory to disturbances such as electrical noise or exposure to alpha particle radiation.
Furthermore, as the DRAM storage capacity increases, the number of cells selected by a word line will generally increase, as well as the number of cells associated with a given bit line. The physical length of the word line and the bit line, relative to its cross sectional area, will also increase accordingly, in turn increasing the series resistance of the word line and the bit line. The access time of a DRAM is directly affected by the series resistance of the word line, as the time required to energize the far end of the word line from the row decoder, and to select the last storage cell, depends upon the RC time constant of the word line as it is driven from the off to the on state. The series resistance of the bit line also impacts the memory access time, as the time required for a storage cell to establish its signal on the bit line depends upon the RC time constant of the bit line. It should be noted that the trend of larger DRAM storage capacity is being accompanied by a trend toward faster access times.
Furthermore, in recent years DRAM devices have been fabricated in lightly-doped epitaxial layers formed on the surface of a substrate, for purposes of noise reduction and increased alpha particle radiation tolerance. However, the use of epitaxy significantly increases the fabrication costs of the device.
Prior DRAM cells have been formed by incorporating both the storage capacitor and the pass gate into a trench. Examples of such DRAM cells are described in copending applications Ser. No. 106,958 filed Oct. 14, 1987, Ser. No. 026,356 filed Mar. 16, 1987, and Ser. No. 153,547 filed Feb. 9, 1988, all assigned to Texas Instruments Incorporated. Particularly, the cells described in said application Ser. No. 026,356 have a word line extending closely along one side of a trench to control conduction in a pass transistor along the side of the trench between a diffused bit line and a buried diffusion. The buried diffusion is connected by way of a buried lateral contact to a polysilicon plug disposed within the trench at the bottom thereat. While the cells of said application Ser. No. 026,356 provide reduced word line capacitance relative to those of application Ser. No. 106,958, for example, the buried lateral contact reduces the scalability of the cell to smaller geometries. Furthermore, the cell of said application Ser. No. 153,547 provides for a cell without a buried lateral contact, but uses polysilicon word lines on all sides of a pillar, causing for high series word line resistance as well as high parasitic capacitance.
It is an object of this invention to provide a DRAM storage cell which provides high storage capacitance per unit of semiconductor surface area.
It is a further object of this invention to provide such a dRAM storage cell which allows for the use of low resistance word lines and bit lines.
It is a further object of this invention to provide such a dRAM storage cell which is scalable.
It is a further object of this invention to provide such a dRAM storage cell which has adequate performance without the use of epitaxy in its formation.
Other objects and advantages of this invention will become apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.